The present invention relates generally to interface or output circuits employed in a semiconductor integrated circuit for driving a transmission line through which circuits are interconnected, and more particularly to a high-speed output driver with an impedance adjustment scheme.
For a high-speed integrated circuit, the output driver design is always a challenge to the circuit designer. The function of an output driver is to provide additional current to drive the next stage of circuits or devices. This drive current needs to be delivered in a manner that does no impair the circuit performance. One measure of circuit performance is the rise/fall time, which is the time required for the output of the circuit to reflect changes in the input. For example, when the input signal transitions from a low logic level to a high logic level, the output also transitions from a low logic level to a high logic level within a predetermined rise time. Similarly, when the input signal transitions from a high logic level to a low logic level, the output also transitions from a high logic level to a low logic level within a predetermined fall time. As can be appreciated, the shorter the rise or fall time, the better the driver performs since the output reflects changes in the input more quickly and in a more responsive fashion than a driver that has a longer rise or fall time. The rise and fall times are also referred to herein as xe2x80x9cpropagation delayxe2x80x9d (i.e., the time or delay needed before changes in the input are reflected in the output).
As applications require higher switching speeds, there is a constant pressure for circuit designers to reduce the propagation delay. One method to decrease the propagation delay is to decrease the output driver impedance. When the output driver impedance is decreased, the rise and fall time can be improved or shortened since more current is provided to charge or discharge the output load, thereby causing the output to reflect changes in the input more quickly.
Unfortunately, when the output driver impedance is decreased, the output driver impedance fails to match the impedance of the load. For example, a typical printed circuit board (PCB) trace has an impedance of 50 ohms to 60 ohms. This impedance mis-match or unmatched impedance causes the output to exhibit ringing. Accordingly, it is important for the output driver to provide sufficient drive current, with minimum ringing and within a predetermined rise/fall time.
To summarize, in order to deliver high current to the load, the output driver has to be at low impedance. However, when the impedance of the output does not match the impedance of the load, which for a typical PC trace is approximately 50 to 60 ohms, noise in the form of ringing (e.g., overshoot and undershoot) in the output. This ringing is undesirable since it increases the bus settling time and degrades the circuit performance.
Furthermore, in most of the high-speed electronic systems, many I/Os are interconnected resulting in large capacitance loading. In order to maintain high switching speed, large output drivers are utilized. Unfortunately, due to the inductive elements [L] of the packaging material and the large current, large noises [Ldi/dt], which are referred to as ground bouncing or VDD bouncing, are generated. This noise causes signal delays, signal degradation, and power supply stability problems.
One of the approaches to partially address the ground bouncing or VDD bouncing problem is described in U.S. Pat. No. 5563542. The ""542 patent provides a scheme that breaks the output driver into two or more small drivers, and turns these drivers on at different times, thereby reducing the di/dt noise. However, this approach only offers limited noise improvement at the cost of slowing down the output speed.
Another approach to partially address the ground bouncing or VDD bouncing problem is described in U.S. Pat. No. 5,959,481. Again, this approach only offers limited noise improvement at the cost of increasing the propagation delay.
Another approach is Gunning Transceiver Logic (GTL) output or RAMBUS logic (RSL) that is well known in the industry. This approach is described in xe2x80x9cPentium Pro Processor GTL+ Guideline,xe2x80x9d AP-524 Intel, March 1996. In this approach, an open drain is connected to an outside resistor that is connected to a power source. When the output level is low, the output level is higher than ground due to parallel termination resistors. This reduced voltage swing improves speed and an 800 Mhz I/O speed can be achieved.
Unfortunately, this approach has the following drawbacks: 1) during output high, there are still noises generated (both overshoot and undershoot) of the supply voltage of the power source, commonly known as ringing, and 2) this approach has a large power dissipation. The output high noise degrades the speed. The large DC current is dissipated or wasted when the output is low. For example in a RAMBUS system, a 25 ohm resistor is typically used, resulting in a 0.9 volt output low dissipating 36 mA per I/O driver. For a RAMBUS chip where there are 18 I/Os, 540 mA or 1.2 Watt of power is dissipated. This power causes the chip to run xe2x80x9chot.xe2x80x9d When the temperature of the chip increases, the chip performance decreases, and the chip is less reliable.
Another approach is known as the HSTL logic (High Speed Transceiver Logic) that is described in Electronic Industries Association (EIA), JEDEC Standard No. 8-6 (JESD8-6), August 1995. In this approach the output swing is reduced by a 50-ohm resistor connected to a voltage source VDD/2. Higher speed is achieved due to the reduced voltage swing. The reduced voltage in turn reduces the Vss and Vcc noise. However, this approach also has the disadvantage of large power dissipation and the problems stemming therefrom.
FIG. 1 depicts a typical CMOS low impedance output driver driving a 50 ohms transmission line and a capacitance load. This scheme provides an output with ringing. FIG. 2 depicts a CMOS low impedance driver with a 25-ohm series-terminating resistor to drive an output load. This scheme adjusts the output impedance to match the load impedance. Accordingly, this scheme provides a relatively clean output with almost no ringing. However, the increased output impedance causes this scheme to have a longer propagation delay that does not meet the rise and fall time requirements of certain high-speed applications.
Accordingly, there remains a need for an output driver circuit that reduces overshoot and undershoot noise to acceptable levels while meeting timing requirements and that overcomes the disadvantages set forth previously.
It is one object of the present invention to provide an output circuit that has high switching speeds.
It is yet another object of the present invention to provide an output circuit that is lower in switching noise.
It is yet another object of the present invention to provide an output circuit that dissipates less power.
It is yet another object of the present invention to provide an output circuit that minimizes overshoot and undershoot noise.
It is yet another object of the present invention to provide an output circuit that provides sufficient drive current to achieve fast slew rates and meet stringent timing requirements.
It is yet another object of the present invention to provide an output circuit that improves the impedance match between the output circuit and the impedance of the transmission-line load.
It is another object of the present invention to provide an output circuit whose output speed is less sensitive to output capacitance loading.
A dynamic impedance adjustment circuit for meeting strict timing requirements while reducing overshoot and undershoot noise to acceptable levels is provided. The dynamic impedance adjustment circuit has a first input for receiving an input signal, a second input for receiving an enable signal, and an output coupled to an output node. The dynamic impedance adjustment circuit has an output driver, coupled to receive the input signal and the enable signal, for selectively providing source or sink current to a load. The dynamic impedance adjustment circuit also has a variable impedance output driver, coupled to the output node, for detecting transitions in the input signal from a logic low level to a logic high level or from a logic high level to a low logic level and selectively provides additional source or sink current, respectively, for a predetermined time. An impedance adjustment control circuit is coupled to the variable impedance output driver for controlling the operation of the variable impedance output driver based on the input signal, enable signal, and the output node.
In one embodiment, the impedance adjustment control circuit utilizes an output feedback driver that is coupled to the output node, a one-shot circuit for generating a one-shot output signal, and a pre-driver preset circuit that operates based on the one-shot output signal. The output feedback driver also includes a transmission gate that operates based on a modified input signal that is derived from the input signal and the enable signal.
In an alternative embodiment, the impedance adjustment control circuit utilizes an output feedback driver coupled to the output node and a pre-driver preset circuit that operates based on the input signal. The output feedback driver also includes a transmission gate that operates based on the input signal.
In yet another alternative embodiment, the impedance adjustment control circuit utilizes an delay input driver that operates based on a delayed version of the input signal and a pre-driver preset circuit that operates on the input signal. The delay input driver also includes a transmission gate that operates based on the input signal.